Ph.D. Researcher · University of Illinois Chicago
Ph.D. student in Electrical and Computer Engineering at UIC, working on machine learning for EDA and VLSI physical design. Building scalable, hardware-aware ML systems across the routing flow, backed by hands-on RTL-to-GDSII experience in Cadence and OpenROAD.
I am a Ph.D. student in Electrical and Computer Engineering at the University of Illinois Chicago (UIC), currently working at the HiPerCAS Lab under the supervision of Dr. Inna Partin-Vaisband. My research lies at the intersection of AI and Electronic Design Automation (EDA) for VLSI circuits.
My flagship projects — GANGR (GAN-Assisted Global Routing Parallelization) and PARGR (Scalable Hardware-Aware Partitioning for Global Routing) — address critical scalability and memory bottlenecks in state-of-the-art IC design tools, achieving up to 40% runtime improvement and 75.4% VRAM reduction on large-scale benchmarks. I am also developing a graph neural network for pre-route prediction of rerouting-critical nets in VLSI detailed routing, using router-generated labels and a net-adjacency graph to capture regional congestion — outperforming per-net baselines on a severely imbalanced classification task. In addition, I have hands-on RTL-to-GDSII experience in Cadence and OpenROAD.
Beyond EDA, I implemented and trained a 124M-parameter GPT-2 from scratch, and designed Inception-YOLO, an object detection model that reduces computational cost by 30–60% while preserving accuracy, and have extensive experience with LDPC channel coding, digital hardware design, and intelligent prediction systems.
